The present invention relates to delay circuits generally and, more particularly, to a delay circuit used with a voltage controlled oscillator to allow alternative phase steps to be implemented.
Conventional approaches to implementing a delay generation circuit include tapping the oscillator to provide waveforms that are equally spaced in time given a reference period of operation. FIG. 1 illustrates a circuit 10 illustrating such a conventional approach. The circuit 10 generally comprises a ring oscillator 12, an analog multiplexer 14, an analog multiplexer 16 and an analog mixer 20. By correctly selecting the settings of the multiplexers 14 and 16, the two adjacent edges of the ring oscillator 12 can be supplied to the analog mixer 20. By controlling the mixer 20, a delay having a magnitude between the two edges supplied to the mixer 20 can be achieved.
While the circuit 10 may provide the desired output, it may also create a long output path from the ring oscillator 12 to an output 22 of the analog mixer 20. Additionally, by implementing two stages of analog devices (i.e., the analog multiplexers 14 and 16 and the analog mixer 20) circuit area and power consumption may be increased. Such an increase in power supply requirements may create additional sources that may inject jitter into the signal being mixed. The analog mixer 20 can also be affected by parasitic coupling when the multiplexers 14 and 16 are switched, which may lead to even larger contributions to signal jitter.
Referring to FIG. 2, a more detailed diagram of the analog multiplexer 14 (or 16) is shown. The analog multiplexer 14 shows differential inputs. The analog multiplexer 14 comprises a transistor 30, a transistor 32, a transistor 34, a transistor 36, a transistor 38, a transistor 40, a resistor 42 and a resistor 44. The transistors 30 and 32 receive select signals (i.e., SEL1b and SEL2b) at their respective gates. Only one of the transistors 30 or 32 is activated at a particular time, otherwise mixing of the signals would occur, which is not consistent with the function of a multiplexer. The multiplexer 16 generally presents a signal OUT and a complement signal OUTb that correspond to one of the input signals IN1 and IN2. The signals OUT and OUTb are selected in response to the select signals SEL1b and SEL2b. 
Referring to FIG. 3, an example of an analog mixer 20 is shown. The analog mixer 20 generally comprises a current source I1, a current source I2, a transistor 50, a transistor 52, a transistor 54, a transistor 56, a transistor 58 and a transistor 60. The mixer 20 presents an output OUT and a complement output OUTb. The mixer 20 generally includes a parasitic capacitance between the input nodes (e.g., IN1 and IN2) and the output nodes (e.g., OUT and OUT). In an ideal implementation, no signal would leak from the input IN2 to the output OUT. However, the parasitic capacitance couples a portion of the signal IN2 to the output. The parasitic coupling can create jitter if the signal on IN2 is switched, as it might be when the multiplexer 20 is switched in a typical operation. In addition, in the implementation shown in FIG. 1, the outputs of the mixer 20 (i.e., OUT and OUTb) may add more noise in a system that is already susceptible to noise injection.
The present invention concerns an apparatus for combining stages of a multiplexer and a mixer into a single stage. The apparatus comprises a first circuit configured to generate a first output signal in response to (i) one or more a input signals and (ii) one or more first select signals, a second circuit configured to generate a second output signal in response to (i) one or more input signals and (ii) one or more second select signals, and a first and second mix signal configured to provide a third output signal in response to the first and second output signals. The third output signal comprises a portion of the first and second output signals controlled by the first and second mix signals.
The objects, features and advantages of the present invention include providing a circuit that combines features a multiplexer and a mixer to (i) eliminate one stage or circuitry, (ii) save in the power consumption of the circuit and (iii) save in the area required to the implement the circuit. Since fewer nodes may be required, the chance of jitter introduction is reduced. Additionally, coupling from an input to the output does not change in response to the particular input selected.